\doxysection{PWR\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_p_w_r___type_def}{}\label{struct_p_w_r___type_def}\index{PWR\_TypeDef@{PWR\_TypeDef}}


Power Control.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a50f96f92968bc5b9b40b870531dde182}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a682b6c3f4af70d7faf280b2e65b3d4a4}{CSR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a8426bae04fc4cae7425f07c50f2359ec}{CR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a5b7c92606919491fb50de53447078fd4}{CR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_accb03e795c571cf5db2c3827ab7329b4}{CPUCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a0af78d1aac1a6f0793f6cef9f2695cdb}{RESERVED0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_af60b520f33b6acfffd301d205f487cef}{D3\+CR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_ace3487dfe91fb691a96a76a048ccb887}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a2e3e128a82d90702992e10086b230e10}{WKUPCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_a73a21c4e6e9dc0fd4f119247c78963a1}{WKUPFR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_w_r___type_def_aa4f0cbb60ffc8af7e3f90f11a6fa120a}{WKUPEPR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Power Control. 

\label{doc-variable-members}
\Hypertarget{struct_p_w_r___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_p_w_r___type_def_accb03e795c571cf5db2c3827ab7329b4}\index{PWR\_TypeDef@{PWR\_TypeDef}!CPUCR@{CPUCR}}
\index{CPUCR@{CPUCR}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CPUCR}{CPUCR}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_accb03e795c571cf5db2c3827ab7329b4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+CPUCR}

PWR CPU control register, Address offset\+: 0x10 \Hypertarget{struct_p_w_r___type_def_a50f96f92968bc5b9b40b870531dde182}\index{PWR\_TypeDef@{PWR\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a50f96f92968bc5b9b40b870531dde182} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+CR1}

PWR power control register 1, Address offset\+: 0x00 \Hypertarget{struct_p_w_r___type_def_a8426bae04fc4cae7425f07c50f2359ec}\index{PWR\_TypeDef@{PWR\_TypeDef}!CR2@{CR2}}
\index{CR2@{CR2}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR2}{CR2}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a8426bae04fc4cae7425f07c50f2359ec} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+CR2}

PWR power control register 2, Address offset\+: 0x08 \Hypertarget{struct_p_w_r___type_def_a5b7c92606919491fb50de53447078fd4}\index{PWR\_TypeDef@{PWR\_TypeDef}!CR3@{CR3}}
\index{CR3@{CR3}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR3}{CR3}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a5b7c92606919491fb50de53447078fd4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+CR3}

PWR power control register 3, Address offset\+: 0x0C \Hypertarget{struct_p_w_r___type_def_a682b6c3f4af70d7faf280b2e65b3d4a4}\index{PWR\_TypeDef@{PWR\_TypeDef}!CSR1@{CSR1}}
\index{CSR1@{CSR1}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR1}{CSR1}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a682b6c3f4af70d7faf280b2e65b3d4a4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+CSR1}

PWR power control status register 1, Address offset\+: 0x04 \Hypertarget{struct_p_w_r___type_def_af60b520f33b6acfffd301d205f487cef}\index{PWR\_TypeDef@{PWR\_TypeDef}!D3CR@{D3CR}}
\index{D3CR@{D3CR}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3CR}{D3CR}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_af60b520f33b6acfffd301d205f487cef} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+D3\+CR}

PWR D3 domain control register, Address offset\+: 0x18 \Hypertarget{struct_p_w_r___type_def_a0af78d1aac1a6f0793f6cef9f2695cdb}\index{PWR\_TypeDef@{PWR\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a0af78d1aac1a6f0793f6cef9f2695cdb} 
uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+RESERVED0}

Reserved, Address offset\+: 0x14 \Hypertarget{struct_p_w_r___type_def_ace3487dfe91fb691a96a76a048ccb887}\index{PWR\_TypeDef@{PWR\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_ace3487dfe91fb691a96a76a048ccb887} 
uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, Address offset\+: 0x1C \Hypertarget{struct_p_w_r___type_def_a2e3e128a82d90702992e10086b230e10}\index{PWR\_TypeDef@{PWR\_TypeDef}!WKUPCR@{WKUPCR}}
\index{WKUPCR@{WKUPCR}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WKUPCR}{WKUPCR}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a2e3e128a82d90702992e10086b230e10} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+WKUPCR}

PWR wakeup clear register, Address offset\+: 0x20 \Hypertarget{struct_p_w_r___type_def_aa4f0cbb60ffc8af7e3f90f11a6fa120a}\index{PWR\_TypeDef@{PWR\_TypeDef}!WKUPEPR@{WKUPEPR}}
\index{WKUPEPR@{WKUPEPR}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WKUPEPR}{WKUPEPR}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_aa4f0cbb60ffc8af7e3f90f11a6fa120a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+WKUPEPR}

PWR wakeup enable and polarity register, Address offset\+: 0x28 \Hypertarget{struct_p_w_r___type_def_a73a21c4e6e9dc0fd4f119247c78963a1}\index{PWR\_TypeDef@{PWR\_TypeDef}!WKUPFR@{WKUPFR}}
\index{WKUPFR@{WKUPFR}!PWR\_TypeDef@{PWR\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WKUPFR}{WKUPFR}}
{\footnotesize\ttfamily \label{struct_p_w_r___type_def_a73a21c4e6e9dc0fd4f119247c78963a1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PWR\+\_\+\+Type\+Def\+::\+WKUPFR}

PWR wakeup flag register, Address offset\+: 0x24 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
